Currently, a test process will be performed to test whether thin film transistors (TFT) for controlling the display of the respective pixels in a liquid crystal display panel work well or not when a liquid crystal display panel (LCD panel) has been produced. Therefore, the layout of a test circuit should be arranged around the liquid crystal display panel, and mostly, in the manner of the shorting-bar layout.
A schematic view of a conventional thin film transistor substrate (TFT substrate) having a test circuit with the shorting-bar layout is shown in FIG. 1. In FIG. 1, the reference number 2 represents gate lines, the reference number 3 represents data lines, the reference number 4 represents gate terminals, the reference number 5 represents data terminals, the reference number 21 represents gate leads, the reference number 26 represents data leads, the reference numbers 22, 23 represent gate shorting bars, the reference numbers 27, 28 represent data shorting bars, and the reference number 10 represents thin film transistors for controlling the display of the respective pixels. The thin film transistor substrate is formed by intersecting perpendicularly a plurality of gate lines 2 connected with the gate driving terminal G and a plurality of data lines 3 connected with the data driving terminal D. The gate lines 2 and the data lines 3 are used for transferring the scan signals and the data signals (so both the gate lines and the data lines can be referred to as the signal lines), respectively, and the thin film transistors 10 for controlling the display of the respective pixels are disposed at the positions where a plurality of gate lines 2 and a plurality of data lines 3 intersect perpendicularly. The gate lines 2 are connected with the gate leads 21 via the gate terminals 4, and are connected to the a peripheral test circuit by using the corresponding gate shorting bars; the data lines 3 are connected with the data leads 26 via the data terminals 5, and are connected to the peripheral test circuit by using the corresponding data shorting bars. Herein, the adjacent gate leads are connected with different gate shorting bars, respectively, and the adjacent data leads are connected with different data shorting bars, respectively. After completing the test of the thin film transistor substrate, the peripheral test circuit is cut off along the cut off line 20 (including the gate terminal side and the data terminal side) as shown in FIG. 1 for performing the subsequent processes.
An enlarged plan view for illustrating the region near the gate terminal 4 is shown in FIG. 2A, and a section plan taken along a straight line I-I in FIG. 2A is shown in FIG. 2B. As shown in FIG. 2A and FIG. 2B, single layer metal of molybdenum, is used as the material of the gate lines. In the procedures for producing the gate line 2, the gate terminal 4 and the gate lead 21 are integrated on a glass substrate 1. Then, a gate insulation layer 6 is deposited, and an active layer 7 and an Ohm contact layer 14 are deposited sequentially on the gate insulation layer 6. After that, a source 8, a drain 9 and gate shorting bars 22, 23 (they are not shown herein, but the gate insulation layer above the end of the gate lead 21 is etched locally to form a through hole which allows the gate shorting bars to be connected electrically with the gate lead for testing the TFT substrate) are formed by using the single molybdenum layer. Next, a passivation layer 11 is deposited, and a gate end electrode 13 is formed by using the material of indium tin oxide (ITO), and the gate end electrode 13 is connected electrically with the gate terminal 4 via a contact hole 12. Finally, the gate leads 21 between the gate shorting bars and the gate terminals 4 are cut off along the cut off line 20 in order to separate the thin film transistor substrate from the peripheral test circuit.
It should be noted that after the gate leads 21 between the gate shorting bars and the gate terminals 4 are cut off, the section of the gate leads 21 is exposed in the air, therefore the vapor in the air will enter the section of the gate leads, while the metal molybdenum used for forming the gate leads 21 is a metal which is easy to be corroded, that is, it is likely that the metal is easily corroded on the section of the gate leads 21, as shown in FIG. 3. Moreover, the corrosion will spread further to the gate terminals 4 even to corrode the gate lines, thus the quality of the LCD panel will be affected. In addition to the single molybdenum layer, the single aluminum layer, molybdenum/aluminum composite layer used cannot satisfy the quality requirement for the TFT substrate either, due to being vulnerable to be corroded in the air. Also, the metal corrosion may happen near the data terminals of the thin film transistor substrate, similar to the metal corrosion produced near the gate terminal.